ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 46

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

Interrupts
Caution:
10.3
Note:
46/171
An external interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
The type of sensitivity defined in the
ei source. In case of a NANDed source (as described in
on an I/O pin configured as input with interrupt, masks the interrupt request even in case of
rising-edge sensitivity.
Peripheral interrupts
Different peripheral interrupt flags in the status register are able to cause an interrupt when
they are active if both:
●
●
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by:
●
●
The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being
enabled) will therefore be lost if the clear sequence is executed.
Figure 19. Interrupt processing flowchart
FROM RESET
The I bit of the CC register is cleared.
The corresponding enable bit is set in the control register.
Writing “0” to the corresponding bit in the status register or
Access to the status register while the flag is set followed by a read or write of an
associated register.
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
FETCH NEXT INSTRUCTION
External interrupt control register (EICR)
N
I BIT SET?
IRET?
Y
Y
N
LOAD PC FROM INTERRUPT VECTOR
Section 12: I/O
N
STACK PC, X, A, CC
INTERRUPT
PENDING?
SET I BIT
Y
ports), a low level
applies to the
ST7DALIF2