ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 40

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

Supply, reset and clock management
9.6.5
9.7
Note:
9.7.1
40/171
Internal watchdog RESET
The RESET sequence generated by a internal Watchdog counter overflow is shown in
Figure
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least t
Figure 15. RESET sequences
System integrity management (SI)
The System Integrity Management block contains the Low voltage Detector (LVD) and
Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to
Low voltage detector (LVD)
The Low Voltage Detector function (LVD) generates a static reset when the V
voltage is below a V
as the power-down keeping the ST7 in reset.
The V
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
current on the supply (hysteresis).
WATCHDOG
RESET
EXTERNAL
RESET
SOURCE
RESET PIN
V
V
IT-(LVD)
IT+(LVD)
IT-(LVD)
15.
Illegal Opcode Reset on page 124
reference value for a voltage drop is lower than the V
V
RUN
DD
IT-(LVD)
ACTIVE PHASE
reference value. This means that it secures the power-up as well
RESET
w(RSTL)out
LVD
.
RUN
t
for further details.
h(RSTL)in
WATCHDOG UNDERFLOW
ACTIVE
PHASE
EXTERNAL
RESET
INTERNAL RESET (256 or 4096 T
VECTOR FETCH
IT+(LVD)
RUN
ACTIVE
PHASE
WATCHDOG
reference value
RESET
t
w(RSTL)out
DD
ST7DALIF2
supply
RUN
CPU
)