ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 33

no-image

ST7DALIF2

Manufacturer Part Number
ST7DALIF2
Description
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7DALIF2

8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention
20 years at 55°C.
256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55°C.
Clock Sources
Internal 1% RC oscillator, crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt
ST7DALIF2
Note:
Caution:
9.3
1
2
3
4
Table 9.
Section 20: Electrical characteristics on page 127
and accuracy of the RC oscillator.
To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100nF, between the V
device.
These two bytes are systematically programmed by ST, including on FASTROM devices.
Consequently, customers intending to use FASTROM service must not use these two bytes.
RCCR0 and RCCR1 calibration values will be erased if the readout protection bit is reset
after it has been set. See
If the voltage or temperature conditions change in the application, the frequency may need
to be recalibrated.
Refer to application note AN1324 for information on how to calibrate the RC frequency using
an external reference signal.
Phase locked loop
The PLL can be used to multiply a 1 MHz frequency from the RC oscillator or the external
clock by 4 or 8 to obtain f
factor of 4 or 8 is selected by 2 option bits.
Refer to
If the PLL is disabled and the RC oscillator is enabled, then f
If both the RC oscillator and the PLL are disabled, f
The x4 PLL is intended for operation with V
The x8 PLL is intended for operation with V
RCCR0
RCCR1
RCCR
Section 22.1 on page 161
RC control registers
OSC2
Readout protection on page 21
of 4 or 8 MHz. The PLL is enabled and the multiplication
f
Conditions
RC
f
RC
T
T
V
V
A
A
=700KHz
DD
DD
for the option byte description.
=25°C
=1MHz
=25°C
=5V
=3V
DD
and V
DD
DD
SS
for more information on the frequency
in the 3.3 V to 5.5 V range
in the 2.4 V to 3.3 V range
OSC
Supply, reset and clock management
pins as close as possible to the ST7
is driven by the external clock.
OSC2 =
ST7DALI address
and FFDEh
and FFDFh
1 MHz.
1000h
1001h
33/171

Related parts for ST7DALIF2