ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 55

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

ST7DALIF2
Note:
As soon as Active-halt is enabled, executing a HALT instruction while the Watchdog is active
does not generate a RESET.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Figure 25. Active-halt timing overview
Figure 26. Active-halt mode flowchart
Notes:
1. 1. This delay occurs only if the MCU exits Active-halt mode by means of a RESET.
2. Peripherals clocked with an external clock source can still be active.
3. Only the RTC1 interrupt and some specific interrupts can exit the MCU from Active-halt mode. Refer to
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
Table 15: Interrupt mapping on page 47
during the interrupt routine and cleared when the CC register is popped.
[Active-halt enabled]
(AWUCSR.AWUEN=0)
HALT INSTRUCTION
INSTRUCTION
(Active-halt enabled)
RUN
N
HALT
INTERRUPT
ACTIVE
HALT
Y
for more details.
256 OR 4096 CPU
CYCLE DELAY
INTERRUPT
3)
RESET
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
FETCH RESET VECTOR
OR
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
I BIT
I BIT
I BIT
N
CYCLE
1)
RESET
Y
VECTOR
FETCH
DELAY
RUN
2)
2)
OFF
OFF
OFF
ON
ON
ON
X
ON
ON
ON
X
0
4)
4)
Power saving modes
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