ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 70

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

Watchdog timer (WDG)
Note:
13.4
13.4.1
13.5
70/171
1
2
the watchdog is disabled. The value to be stored in the CR register must be between FFh
and C0h (see
●
●
●
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
If the watchdog is activated, the HALT instruction will generate a Reset.
Table 34.
The timing variation shown in
writing to the CR register.
The number of CPU clock cycles applied during the RESET phase (256 or 4096) must be
taken into account in addition to these timings.
Hardware watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the CR is not used.
Refer to the Option Byte description in
Using Halt mode with the WDG (WDGHALT option)
If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
The same behavior occurs in Active-halt mode.
Interrupts
None.
.
The WDGA bit is set (watchdog enabled)
The T6 bit is set to prevent generating an immediate reset
The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset.
WDG counter code
Watchdog timing (f
Table
C0h
FFh
34):
Table 34
CPU
= 8 MHz.)
Section 22.1 on page
is due to the unknown status of the prescaler when
[ms]
min
127
1
161.
[ms]
max
128
2
ST7DALIF2