ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 169

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

ST7DALIF2
Table 100. Document revision history (continued)
19-Nov-2004
Date
Revision
2
Reset delay in section 11.1.3 on page 51 changed to 30 µs
Altered note 1 for section 13.2.3 on page 101 removing references to
RESET
Removed sentence relating to an effective change only after overflow
for CK[1:0],
MOD00 replaced by 0Ex in
Added Note 2 related to Exit from Active halt,
59
Added illegal opcode detection to page 1,
section 12 on page 94
Clarification of Flash readout protection,
Added note 4 and description relating to Total Percentage in Error
and Amplifier Output Offset
Variation to the ADC Characteristics subsection and table,
Added note 5 and description relating to Offset Variation in
Temperature to ADC Characteristics subsection and table,
FPLL value of 1MHz quoted as Typical instead of a Minimum in
section 13.3.4.1 on page 104
Updated FSCK in
Corrected f
page 108
Max values updated for ADC Accuracy,
Notes indicating that PB4 cannot be used as an external interrupt in
HALT mode,
on page 138
Changed
Changed
Removed “optional” referring to VDD in
Changed FMP_R option bit description in
Added “Clearing active interrupts outside interrupt routine” on page
138
Changed “Development Tools” on page 134
Changed
section 11.5.2 on page 79
section 11.5.3.3 on page 82
Figure 41 on page
CPU
page 60
section 16.6
and
in Slow and slow wait modes in
Section 8.3 PERIPHERAL INTERRUPTS
section 13.10.1 on page 121
Figure 36 on page 57
70: f
Changes
CPU
instead of 8 MHz f
Figure 4 on page 13
page 124
section 4.5.1 on page 14
section 15.1 on page 130
section 7.6 on page
section 11.2.5 on page
to f
section 13.4.1 on
Revision history
CPU
/4 and f
CPU
page 126
page 126
169/171
CPU
29,
/2