ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 52

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

Power saving modes
11.4
52/171
Figure 22. Wait mode flowchart
1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘HALT’ instruction when Active-Halt is disabled (see
for more details) and when the AWUEN bit in the AWUCSR register is cleared.
The MCU can exit Halt mode on reception of either a specific interrupt (see
Interrupt mapping on page
or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay
is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by
servicing the interrupt or by fetching the reset vector which woke it up (see
When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a Watchdog RESET (see
more details).
during the interrupt routine and cleared when the CC register is popped.
47) or a RESET. When exiting Halt mode by means of a RESET
WFI INSTRUCTION
N
INTERRUPT
Y
OR SERVICE INTERRUPT
FETCH RESET VECTOR
256 OR 4096 CPU CLOCK
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BIT
N
CYCLE DELAY
RESET
Y
OFF
OFF
Section 22.1 on page 161
ON
ON
ON
ON
ON
ON
ON
X
0
0
1)
Section 11.5 on page 54
Figure
Table 15:
ST7DALIF2
24).
for