ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 7
ST7DALIF2
Manufacturer Part Number
ST7DALIF2
Description
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
Manufacturer
STMicroelectronics
Datasheet
1.ST7DALIF2.pdf
(171 pages)
Specifications of ST7DALIF2
8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention
20 years at 55°C.
256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55°C.
Clock Sources
Internal 1% RC oscillator, crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt
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ST7DALIF2
18
19
17.5
17.6
17.7
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
18.1
18.2
18.3
18.4
18.5
18.6
18.7
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
19.1
17.4.4
17.4.5
17.4.6
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
17.5.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
17.7.1
17.7.2
17.7.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
18.3.1
18.3.2
18.3.3
18.3.4
Changing the conversion channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
18.7.1
18.7.2
18.7.3
CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
19.1.1
19.1.2
19.1.3
19.1.4
19.1.5
19.1.6
19.1.7
Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Single master and multimaster configurations . . . . . . . . . . . . . . . . . . . 107
Using the SPI to wake-up the device from Halt mode . . . . . . . . . . . . . 108
Control register (SPICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Control/status register (SPICSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Data I/O register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Analog power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Input voltage amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Digital A/D conversion result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
A/D conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Control/status register (ADCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Data register high (ADCDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
AMP control/data register low (ADCDRL) . . . . . . . . . . . . . . . . . . . . . . 117
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Contents
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