ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 136

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

Electrical characteristics
20.4.1
136/171
Figure 63. Typical I
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
2.0
Supply current
T
Table 72.
1. CPU running with memory access, all I/O pins in input mode with a static value at V
2. All I/O pins in input mode with a static value at V
3. Slow mode selected with f
4. Slow-Wait mode selected with f
5. All I/O pins in output mode with a static value at V
6. All I/O pins in input mode with a static value at V
7. This consumption refers to the Halt period only and not the associated run period which is software
Symbol
2.5
A
= -40 to +85° C unless otherwise specified, V
I
peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
input (CLKIN) driven by external square wave, LVD disabled.
at V
LVD disabled.
value at V
wave, LVD disabled.
characterization results, tested in production at V
and f
dependent.
8Mhz
4Mhz
1Mhz
DD
3.0
DD
CPU
or V
3.5
DD
Supply current in RUN mode
Supply current in Wait mode
Supply current in Slow mode
Supply current in Slow Wait
mode
Supply current in Halt mode
Supply current in AWUFH
mode
max.
DD
Vdd (V)
SS
in RUN vs. f
Supply current characteristics
4.0
or V
(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave,
(6)(7)
SS
4.5
Parameter
(no load), all peripherals in reset state; clock input (CLKIN) driven by external square
5.0
CPU
CPU
5.5
based on f
CPU
6.0
based on f
(5)
OSC2
External Clock, f
Internal RC, f
f
External Clock, f
Internal RC, f
f
f
f
-40° C≤T
T
T
CPU
CPU
CPU
CPU
Figure 64. Typical I
A
A
OSC2
divided by 32. All I/O pins in input mode with a static value
= +125° C
= +25° C
DD
DD
DD
=8 MHz
=8 MHz
=250 kHz
=250 kHz
SS
or V
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
or V
divided by 32. All I/O pins in input mode with a static
max and f
(no load), LVD disabled. Data based on
A
SS
SS
≤+85° C
DD
Conditions
2
(no load). Data tested in production at V
(no load), all peripherals in reset state; clock
(1)
(2)
=5.5 V
CPU
CPU
(3)
(4)
CPU
2.5
CPU
CPU
=1 MHz
=1 MHz
250Khz
125Khz
62.5Hz
max.
=1 MHz
=1 MHz
3
DD
3.5
(1)
(2)
in Slow vs. f
Vdd (V)
4
DD
2.2
1.8
1
7.5
0.8
3.7
1.6
1.6
1
15
20
Typ
4.5
or V
SS
5
12
6
2.5
2.5
10
50
30
Max
(no load), all
CPU
ST7DALIF2
5.5
DD
max.
Unit
mA
6
μA