ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 131

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

ST7DALIF2
20.3.1
20.3.2
20.3.3
Operating conditions with low voltage detector (LVD)
T
Table 66.
1. Not tested in production.
2. Not tested in production. The V
3. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the
Auxiliary Voltage Detector (AVD) Thresholds
T
Table 67.
1.
Internal RC oscillator and PLL
The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by
option byte).
V
V
V
Vt
t
I
V
Symbol
Symbol
A
A
V
g(VDD)
DD(LVD
IT+
IT-
hys
IT+
IT-
ΔV
POR
V
= -40 to 85°C, unless otherwise specified
= -40 to 85°C, unless otherwise specified
and LVD reset. When the V
MCU.
application, it is recommended to pull V
example in
Not tested in production.
(LVD)
hys
(AVD)
(LVD)
(AVD)
IT-
)
Reset release threshold
(V
Reset generation threshold
(V
LVD voltage threshold
hysteresis
V
Filtered glitch delay on V
LVD/AVD current consumption
1=>0 AVDF flag toggle
threshold
(V
0=>1 AVDF flag toggle
threshold
(V
AVD voltage threshold
hysteresis
Voltage drop between AVD
flag set and LVD reset
activation
DD
DD
DD
DD
DD
Figure 87 on page 150
Power on/power down operating conditions
AVD thresholds
rise time rate
rise)
fall)
rise)
fall)
Parameter
Parameter
DD
(2)(3)
slope is outside these values, the LVD may not ensure a proper reset of the
DD
rise time rate condition is needed to insure a correct device power-on
and note 4.
DD
DD
down to 0V to ensure optimum restart conditions. Refer to circuit
High Threshold
Med. Threshold
Low Threshold
High Threshold
Med. Threshold
Low Threshold
V
Not detected by the
LVD
High Threshold
Med. Threshold
Low Threshold
High Threshold
Med. Threshold
Low Threshold
V
V
IT+
IT+
DD
(LVD)
(AVD)
fall
Conditions
Conditions
-V
-V
IT-
IT-
(LVD)
(AVD)
3.40
2.65
4.00
4.40
3.90
3.20
3.80
3.20
2.40
Min
4.30
3.70
2.90
Min
20
(1)
(1)
Electrical characteristics
(1)
(1)
(1)
(1)
4.70
4.10
3.40
4.60
3.90
3.20
0.45
4.25
3.60
2.90
4.05
3.40
2.70
Typ
150
Typ
200
220
4.30
3.65
2.90
4.90
4.10
3.40
20000
Max
4.50
3.80
3.15
Max
5.00
4.30
3.60
150
(1)
(1)
(1)
(1)
(1)
(1)
131/171
μs/V
Unit
Unit
mV
mV
μA
ns
V
V
V