ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 53

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

ST7DALIF2
Figure 23. Halt mode timing overview
Figure 24. Halt mode flowchart
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
5. If the PLL is enabled by option byte, it outputs the clock after a delay of t
Table 15: Interrupt mapping
during the interrupt routine and cleared when the CC register is popped.
[Active Halt disabled]
INSTRUCTION
RUN
(AWUCSR.AWUEN=0)
HALT INSTRUCTION
HALT
(Active-halt disabled)
N
WATCHDOG
for more details.
WDGHALT
RESET
HALT
1
INTERRUPT
Y
1)
256 OR 4096 CPU
CYCLE DELAY
INTERRUPT
ENABLE
3)
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
RESET
0
FETCH RESET VECTOR
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
I BIT
I BIT
I BIT
OR
N
CYCLE
RESET
Y
WATCHDOG
DELAY
VECTOR
FETCH
DISABLE
2)
OFF
OFF
OFF
OFF
ON
ON
X
5)
ON
ON
ON
X
RUN
0
4)
4)
STARTUP
(see
Power saving modes
Figure
11).
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