ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 110

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

Serial peripheral interface (SPI)
Note:
Note:
Note:
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Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also cleared by hardware when, in master mode,
SS=0 (see
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output and the
functions of the MISO and MOSI pins are reversed.
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. This bit determines the idle state of the serial Clock.
The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
The slave must have the same CPOL and CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These bits are set and cleared by software. Used with the SPR2 bit, they select the baud
rate of the SPI serial clock SCK output by the SPI in master mode.
These 2 bits have no effect in slave mode.
Table 48.
Control/status register (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only).
This bit is set by hardware when a transfer has been completed. An interrupt is generated if
SPIF
7
Master mode fault (MODF) on page
SPI master mode SCK frequency
Serial clock
WCOL
f
f
f
f
CPU
f
f
CPU
CPU
CPU
CPU
CPU
/128
/16
/32
/64
/4
/8
OVR
MODF
SPR2
105).
1
0
0
1
0
0
-
SOD
SPR1
0
0
0
1
1
1
SSM
ST7DALIF2
SPR0
0
0
1
0
0
1
SSI
0