TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 113

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

X: Don’t care, −: No change
TA01RUN
TA01MOD
TA0REG
TA1FFCR
PAFC2
TA01RUN
Example: To output the following PWM waves on the TA1OUT pin at fc = 16 MHz:
overflow is detected when the TA0REG double buffer is enabled.
(value to be compared)
Therefore n should be set to 7.
Since the low-level period is 16.0 μsec when φT1 = (2
set the following value for TA0REG:
In this mode, the value of the register buffer will be shifted into TA0REG if 2
Use of the double buffer facilitates the handling of low duty ratio waves.
Match with TA0REG
To achieve a 64.0-μs PWM cycle by setting φT1 to (2
28.4 μs ÷ (2
16.0 μs ÷ (2
MSB
← –
← 1
← 0
← X
← X
← 1
Register buffer
∗ Clock state
7
2
n
TA0REG
overflow
6
X
1
1
X
X
X
System clock: High-frequency (fc)
Clock gear: 1 (fc)
Prescaler clock: f
Figure 3.7.18 Register Buffer Operation
5
X
1
0
X
X
X
3
3
/fc)s ≈ 128 = 2
/fc)s ≈ 72 = 48H
4
X
0
0
X
X
X
16.0 μs
LSB
3
–
–
1
1
–
–
28.4 μs
Up counter = Q
2
–
–
0
0
–
1
FPH
91C025-111
1
–
0
0
1
1
–
n
Q
Q
0
0
1
0
X
–
1
1
2
1
Stop TMRA0 and clear it to 0.
Select 8-bit PWM mode (cycle: 2
input clock.
Write 48H.
Clear TA1FF to 0, enable the inversion and double buffer.
Set PA1 and the TA1OUT pin.
Start TMRA0 counting.
Shift into TA0REG
3
/fc)s,
3
Up counter = Q
/fc)s (at fc = 36 MHz):
Q
2
TA0REG (Register buffer)
write
2
7
) and select φT1 as the
Q
3
TMP91C025
2007-02-28
n