TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 47

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

DMAM0 to
DMAM3
(fixed)
000
Note 1: n is the corresponding micro DMA channels 0 to 3
Note 2: Execution time is under the condition of:
Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in
000
001
010
011
100
101
0
DMADn+/DMASn+: Post-increment (increment register value after transfer)
DMADn−/DMASn−: Post-decrement (decrement register value after transfer)
The I/Os in the table mean fixed address and the memory means increment (INC) or
decrement (DEC) addresses.
the above table.
0
(4) Detailed description of the transfer mode register
00
01
10
00
01
10
00
01
10
00
01
10
00
01
10
00
16-bit bus width (both translation and destination address area) /0 waits/
fc = 36 MHz/selected high frequency mode (fc × 1)
0
Transfer Bytes
Byte transfer
Word transfer
4-bit transfer
Byte transfer
Word transfer
4-bit transfer
Byte transfer
Word transfer
4-bit transfer
Byte transfer
Word transfer
4-bit transfer
Byte transfer
Word transfer
4-bit transfer
Counter mode
DMASn ← DMASn + 1
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
..................... For counting number of times interrupt is generated
8 bits
Number of
Mode
Transfer destination address INC mode
................................................ I/O to memory
(DMADn+) ← (DMASn)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Transfer destination address DEC mode
................................................ I/O to memory
(DMADn−) ← (DMASn)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Transfer source address INC mode
................................................ Memory to I/O
(DMADn) ← (DMASn+)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Transfer source address DEC mode
................................................ Memory to I/O
(DMADn) ← (DMASn−)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Fixed address mode
........................................................ I/O to I/O
(DMADn) ← (DMASn−)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Note: When setting a value in this register, write 0 to the upper 3 bits.
Mode Description
91C025-45
Execution States
Number of
12 states
12 states
12 states
12 states
12 states
8 states
8 states
8 states
8 states
8 states
5 states
Execution Time
at fc = 36 MHz
Minimum
TMP91C025
2007-02-28
444 ns
667 ns
444 ns
667 ns
444 ns
667 ns
444 ns
667 ns
444 ns
667 ns
278 ns