TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 35

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

(3) Operation
Interrupt for
Figure 3.3.6 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt
Figure 3.3.7 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt
D0 to D15
A0 to A23
a. IDLE2 mode
b. IDLE1 mode
release
for release
D0 to D15
A0 to A23
Interrupt
WR
RD
IDLE2 setting register, can take place. Instruction execution by the CPU stops.
mode halt state by an interrupt.
X1
operate. The system clock in the MCU stops. The pin status in the IDLE1 mode is
depended on setting the register SYSCR2<SELDRV, DRVE>. Table 3.3.6, Table
3.3.7 summarizes the state of these pins in the IDLE mode1.
system clock; however, clearance of the halt state (e.g. restart of operation) is
synchronous with it.
an interrupt.
WR
RD
In IDLE2 mode only specific internal I/O operations, as designated by the
Figure 3.3.6 illustrates an example of the timing for clearance of the IDLE2
In IDLE1 mode, only the internal oscillator and the RTC, MLD continue to
In the halt state, the interrupt request is sampled asynchronously with the
Figure 3.3.7 illustrates the timing for clearance of the IDLE1 mode halt state by
X1
Data
Data
91C025-33
IDLE2
mode
IDLE1
mode
Data
TMP91C025
Data
2007-02-28