TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 159

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

3.10.3
INT2
PB5/INT2 pin
Reset counter for de-bounce time
PB5/INT2 pin
Touch Detection Procedure
SMX).
between X and Y directions in the touch screen are not connected and INT2 isn’t generated.
register (PXD) between X and Y direction in the touch screen are connected and INT2 will
be generated.
interrupt generation though one time touch.
A touch detection procedure is a preparing procedure till a pen touches to the screen.
When the waiting state, ON only SPY-switch and OFF other 3-switch (SMY, SPX and
During this waiting state, PB5/INT2/PX pin’s level is L because of the internal resistors
If the pen touches, PB5/INT2/PX pin’s level is H because of the internal pull-down
And the de-bounce circuit like following diagram is prepared to avoid some number’s
This can ignore the pulse under the time which is set to TSICR1 register.
INT2 is generated by matching counter and
specified de-bounce time.
Start counter for de-bounce time
Figure 3.10.4 Timing Diagram of De-bounce Circuit
Figure 3.10.3 Block Diagram of De-bounce Circuit
De-bounce
TSICR1
De-bounce
time
circuit
INT2 isn’t generated by matching counter and specified de-bounce
time because of it is an edge-type interrupt.
91C025-157
De-bounce
time
TSICR0<TWIEN>, IIMC<I2EDGE>, PBFC<PB5F>
After pen is detouched, INT2 can be issued again.
Falling edge of INT2
F/F
and selects the
Rising edge or
Enables INT2
De-bounce
time
TMP91C025
2007-02-28
INT2
TSICR0
<PTST>