TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 40

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

3.4
Interrupts
interrupt controller.
the CPU.If multiple interrupts are generated simultaneously, the interrupt controller sends the
interrupt with the highest priority to the CPU. (The highest priority is level 7 using for
non-maskable interrupts.)
mask register <IFF2:0>. If the priority level of the interrupt is higher than the value of the
interrupt mask register, the CPU accepts the interrupt.
instruction (EI num sets <IFF2:0> data to num).
interrupt controller is 3 or higher, and also non-maskable interrupts.
instruction is used to disable maskable interrupts because of the priority level of maskable
interrupts is 1 to 6. The EI instruction is vaild immediately after execution.
micro DMA interrupt processing mode as well. The CPU can transfer the data (1/2/4 bytes)
automatically in micro DMA mode, therefore this mode is used for speed-up interrupt
processing, such as transferring data to the internal or external peripheral I/O. Moreover,
TMP91C025 has software start function for micro DMA processing request by the software not
by the hardware interrupt.
Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and by the built-in
The TMP91C025 has a total of 37 interrupts divided into the following three types:
A (fixed) individual interrupt vector number is assigned to each interrupt.
One of six (variable) priority level can be assigned to each maskable interrupt.
The priority level of non-maskable interrupts are fixed at 7 as the highest level.
When an interrupt is generated, the interrupt controller sends the piority of that interrupt to
The CPU compares the priority level of the interrupt with the value of the CPU interrupt
The interrupt mask register <IFF2:0> value can be updated using the value of the EI
For example, specifying EI 3 enables the maskable interrupts which priority level set in the
Operationally, the DI instruction (<IFF2:0> = 7) is identical to the EI 7 instruction. DI
In addition to the above general-purpose interrupt processing mode, TLCS-900/L1 has a
Figure 3.4.1 shows the overall interrupt processing flow.
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•
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Interrupts generated by CPU: 9 sources
Internal interrupts: 23 sources
Interrupts on external pins ( INT0 to INT3, INTKEY): 5 sources
(Software interrupts, illegal instruction interrupt)
91C025-38
TMP91C025
2007-02-28