TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 209

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

Note: Number in above Table shows f
Width
Read
Word
Bus
Byte
Xin-Xout, 1.00 equal 37 ns.
Above table don’t show to guarantee the time, it shows outline. For details, look for AC timing
at after page.
Type
C
C
A
B
A
B
A23 to A0 pin
D7 to D0 pin
RD pin
D1BSCP pin
Mode
Write
Nibble
Nibble
Nibble
Nibble
Nibble
Nibble
Byte
Byte
Byte
Byte
Byte
Byte
Figure 3.14.7 Definition of Specification
Table 3.14.7 Each Type Timing Table
D1BSCP pulse width
Setup Time
Data setup time
0.5x
0.5x
1.0x
1.0x
1.0x
1.0x
0.5x
0.5x
1.0x
1.0x
1.0x
1.0x
N
91C025-208
FPH
D1SCP cycle
clock cycle, for example, in case of 27 MHz frequency
Hold Time
State/cycle
Data hold time
1.0x
1.0x
0.5x
0.5x
2.5x
1.5x
1.0x
1.0x
0.5x
0.5x
1.5x
1.5x
D1BSCP
N + 1
Pulse
Width
1.5x
1.0x
2.0x
1.0x
1.5x
2.5x
1.0x
1.0x
1.0x
1.0x
1.5x
2.5x
D1BSCP
Cycle
4.0x
2.0x
4.0x
2.0x
6.0x
5.0x
2.0x
2.0x
2.0x
2.0x
3.0x
5.0x
TMP91C025
2007-02-28
State/
Cycle
10.0x
10.0x
10.0x
20.0x
4.0x
6.0x
4.0x
6.0x
6.0x
6.0x
6.0x
8.0x