XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 157

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

12.3.9 Timer Interrupt Flag Registers
M68HC12B Family — Rev. 8.0
MOTOROLA
TCRE — Timer Counter Reset Enable Bit
PR2, PR1, and PR0 — Timer Prescaler Select Bits
Read: Anytime
Write: Used in the clearing mechanism; set bits cause corresponding bits to
TFLG1 indicates when interrupt conditions have occurred. To clear a bit in the flag
register, write a 1 to the bit. Writing a logic 0 does not affect current status of the bit.
When TFFCA bit in TSCR register is set, a read from an input capture or a write
into an output compare channel ($90–$9F) causes the corresponding channel flag
CnF to be cleared.
Address: $008E
This bit allows the timer counter to be reset by a successful output compare 7
event.
If TC7 = $0000 and TCRE = 1, TCNT stays at $0000 continuously. If TC7 =
$FFFF and TCRE = 1, TOF never gets set even though TCNT counts from
$0000 through $FFFF.
These three bits specify the number of ÷2 stages that are to be inserted between
the module clock and the timer counter. See
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal 0.
Reset:
Read:
Write:
0 = Counter reset inhibited and counter free runs
1 = Counter reset by a successful output compare 7
be cleared
PR2
0
0
0
0
1
1
1
1
Bit 7
C7F
0
Figure 12-14. Timer Interrupt Flag 1 (TFLG1)
Standard Timer Module (TIM)
C6F
PR1
6
0
0
0
1
1
0
0
1
1
Table 12-3. Prescaler Selection
C5F
5
0
PR0
0
1
0
1
0
1
0
1
C4F
4
0
Table
C3F
3
0
Prescale Factor
Reserved
Reserved
12-3.
Standard Timer Module (TIM)
16
32
1
2
4
8
C2F
2
0
C1F
1
0
Block Diagram
Data Sheet
Bit 0
C0F
0
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