XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 29

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

1.6.3.2 ECLK
1.6.3.3 RESET
1.6.3.4 IRQ
M68HC12B Family — Rev. 8.0
MOTOROLA
ECLK is the output connection for the internal bus clock and is used to demultiplex
the address and data and is used as a timing reference. ECLK frequency is equal
to one half the crystal frequency out of reset.
In normal single-chip mode, the E-clock output is off at reset to reduce the effects
of radio frequency interference (RFI), but it can be turned on if necessary.
In special single-chip mode, the E-clock output is on at reset but can be turned off.
In special peripheral mode, the E clock is an input to the MCU.
All clocks, including the E clock, are halted when the MCU is in stop mode. It is
possible to configure the MCU to interface to slow external memory. ECLK can be
stretched for such accesses.
An active-low, bidirectional control signal, RESET is an input to initialize the MCU
to a known startup state. It also acts as an open-drain output to indicate that an
internal failure has been detected in either the clock monitor or COP watchdog
circuit. The MCU goes into reset asynchronously and comes out of reset
synchronously. This allows the part to reach a proper reset state even if the clocks
have failed, while allowing synchronized operation when starting out of reset.
It is possible to determine whether a reset was caused by an internal source or an
external source. An internal source drives the pin low for 16 cycles; eight cycles
later, the pin is sampled. If the pin has returned high, either the COP watchdog
vector or clock monitor vector is taken. If the pin is still low, the external reset is
determined to be active and the reset vector is taken. Hold reset low for at least 32
cycles to assure that the reset vector is taken in the event that an internal COP
watchdog timeout or clock monitor fail occurs.
IRQ is the maskable external interrupt request pin. It provides a means of applying
asynchronous interrupt requests to the MCU. Either falling edge-sensitive
triggering or level-sensitive triggering is program selectable (interrupt control
register, INTCR). IRQ is always configured to level-sensitive triggering at reset.
When the MCU is reset, the IRQ function is masked in the condition code register.
This pin is always an input and can always be read. In special modes, it can be
used to apply external EEPROM V
is not needed for normal EEPROM program and erase cycles. Because the IRQ
pin is also used as an EEPROM programming voltage pin, there is an internal
resistive pullup on the pin.
General Description
PP
in support of EEPROM testing. External V
Pinout and Signal Descriptions
General Description
Data Sheet
PP
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