XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 249

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

15.9 BDLC Registers
15.9.1 BDLC Control Register 1
M68HC12B Family — Rev. 8.0
MOTOROLA
Eight registers are available for controlling operation of the BDLC and for
communicating data and status information. A full description of each register is
given here.
IMSG — Ignore Message Bit
CLKS — Clock Select Bit
R1 and R0 — Rate Select Bits
This bit disables the receiver until a new start-of-frame (SOF) is detected. The
bit is cleared automatically by the reception of an SOF symbol or a BREAK
symbol. It then generates interrupt requests and allows changes of the status
register to occur. However, these interrupts may still be masked by the interrupt
enable (IE) bit. When set, all BDLC interrupt requests are masked (except $20
in BSVR) and the status bits are held in their reset state. If this bit is set while
the BDLC is receiving a message, the rest of the incoming message is ignored.
For J1850 bus communications to take place, the nominal BDLC operating
frequency (f
bit allows the user to select the frequency (1.048576 MHz or 1 MHz) used to
automatically adjust symbol timing.
These bits determine the amount by which the frequency of the MCU
CGMXCLK signal is divided to form the MUX interface clock (f
defines the basic timing resolution of the MUX interface. They may be written
only once after reset, after which they become read-only bits.
The nominal frequency of f
for J1850 bus communications to take place. Hence, the value programmed
into these bits is dependent on the chosen MCU system clock frequency per
Table
Address: $00F8
Reset:
Read:
Write:
1 = Disable receiver
0 = Enable receiver
1 = Binary frequency, 1.048576 MHz
0 = Integer frequency, 1 MHz
15-2.
IMSG
Byte Data Link Communications (BDLC)
Bit 7
R
1
BDLC
Figure 15-12. BDLC Control Register 1 (BCR1)
) must always be 1.048576 MHz or 1 MHz. The CLKS register
= Reserved
CLKS
6
1
BDLC
R1
5
1
must always be 1.048576 MHz or 1.0 MHz
R0
4
0
Byte Data Link Communications (BDLC)
R
3
0
0
R
2
0
0
BDLC
BDLC Registers
IE
1
0
) which
Data Sheet
WCM
Bit 0
0
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