XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 232

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Byte Data Link Communications (BDLC)
15.5.3 BDLC Stop and CPU Stop Mode
15.6 Loopback Modes
15.6.0.1 Digital Loopback Mode
15.6.0.2 Analog Loopback Mode
Data Sheet
232
NOTE:
This power-conserving mode is entered automatically from run mode when the
WCM bit in the BCR1 register is set followed by a CPU STOP instruction. This is
the lowest-power mode that the BDLC can enter.
In this mode:
The first passive-to-active transition on the J1850 network generates a
non-maskable ($20) CPU interrupt request by the BDLC, allowing the CPU clocks
to restart and the BDLC internal clocks to restart. Therefore, the new message
which wakes up the BDLC from the BDLC stop mode and the CPU from the CPU
wait mode are not received correctly. This is due primarily to the time required for
the MCU’s oscillator to stabilize before the clocks can be applied internally to the
other MCU modules, including the BDLC.
Ensure that all transmissions are complete or aborted prior to putting the BDLC into
stop mode (WCM = 1 in BCR1).
Two loopback modes are used to determine the source of bus faults.
When a bus fault has been detected, the digital loopback mode is used to
determine if the fault condition is caused by failure in the node’s internal circuits or
elsewhere in the network, including the node’s analog physical interface. In this
mode, the transmit digital output pin (BDTxD) and the receive digital input pin
(BDRxD) of the digital interface are disconnected from the analog physical
interface and tied together to allow the digital portion of the BDLC to transmit and
receive its own messages without driving the J1850 bus.
Analog loopback mode is used to determine if a bus fault has been caused by a
failure in the node’s off-chip analog transceiver or elsewhere in the network. The
BDLC analog loopback mode does not modify the digital transmit or receive
functions of the BDLC. It does, however, ensure that once analog loopback mode
is exited, the BDLC waits for an idle bus condition before participation in network
communication resumes. If the off-chip analog transceiver has a loopback mode,
it usually causes the input to the output drive stage to be looped back into the
receiver, allowing the node to receive messages it has transmitted without driving
the J1850 bus. In this mode, the output to the J1850 bus typically is high
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The BDLC internal clocks are stopped.
The CPU internal clocks are stopped.
The BDLC awaits J1850 network activity.
Byte Data Link Communications (BDLC)
M68HC12B Family — Rev. 8.0
MOTOROLA