XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 315

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

18.1 Introduction
18.2 Instruction Queue
M68HC12B Family — Rev. 8.0
MOTOROLA
Data Sheet — M68HC12B Family
Development support involves complex interactions between MCU resources and
external development systems. This section concerns instruction queue and queue
tracking signals, background debug mode, breakpoints, and instruction tagging.
It is possible to monitor CPU activity on a cycle-by-cycle basis for debugging.The
CPU12 instruction queue provides at least three bytes of program information to
the CPU when instruction execution begins. The CPU12 always completely
finishes executing an instruction before beginning to execute the next instruction.
Status signals IPIPE1 and IPIPE0 provide information about data movement in the
queue and indicate when the CPU begins to execute instructions. Information
available on the IPIPE1 and IPIPE0 pins is time multiplexed. External circuitry can
latch data movement information on rising edges of the E-clock signal; execution
start information can be latched on falling edges.
of data on the pins.
1. Refers to data that was on the bus at the previous E falling edge.
2. Refers to bus cycle starting at this E falling edge.
IPIPE[1:0]
IPIPE[1:0]
0:0
0:1
1:0
1:1
0:0
0:1
1:0
1:1
Execution Start — IPIPE[1:0] Captured at Falling Edge of E Clock
Data Movement — IPIPE[1:0] Captured at Rising Edge of E Clock
Development Support
Mnemonic
Mnemonic
Table 18-1. IPIPE Decoding
SOD
ALD
SEV
LAT
ALL
INT
—
—
Section 18. Development Support
No movement
Latch data from bus
Advance queue and load from bus
Advance queue and load from latch
No start
Start interrupt sequence
Start even instruction
Start odd instruction
Table 18-1
Meaning
Meaning
shows the meaning
(1)
(2)
Data Sheet
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