XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 67

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

3.6 Indexed Addressing Modes
3.7 Opcodes and Operands
M68HC12B Family — Rev. 8.0
MOTOROLA
The CPU12 indexed modes reduce execution time and eliminate code size
penalties for using the Y index register. CPU12 indexed addressing uses a
postbyte plus zero, one, or two extension bytes after the instruction opcode. The
postbyte and extensions do these tasks:
The CPU12 uses 8-bit opcodes. Each opcode identifies a particular instruction and
associated addressing mode to the CPU. Several opcodes are required to provide
each instruction with a range of addressing capabilities.
Only 256 opcodes would be available if the range of values were restricted to the
number that can be represented by 8-bit binary numbers. To expand the number
rr0nnnnn
111rr0zs
111rr011
rr1pnnnn
111rr1aa
111rr111
rr: 00 = X, 01 = Y, 10 = SP, 11 = PC
•
•
•
•
Code (xb)
Postbyte
Specify which index register is used
Determine whether a value in an accumulator is used as an offset
Enable automatic pre- or post-increment or decrement
Specify use of 5-bit, 9-bit, or 16-bit signed offsets
,r
n,r
–n,r
n,r
–n,r
[n,r]
n,–r
n,r–
A,r
B,r
D,r
[D,r]
Source Code
Syntax
Central Processor Unit (CPU)
Table 3-2. Summary of Indexed Operations
n,+r
n,r+
5-bit constant offset n = –16 to +15
r can specify X, Y, SP, or PC
Constant offset (9- or 16-bit signed)
z:0 = 9-bit with sign in LSB of postbyte(s)
if z = s = 1, 16-bit offset indexed-indirect (see below)
rr can specify X, Y, SP, or PC
16-bit offset indexed-indirect
rr can specify X, Y, SP, or PC
Auto pre-decrement/increment
or Auto post-decrement/increment;
p = pre-(0) or post-(1), n = –8 to –1, +1 to +8
rr can specify X, Y, or SP (PC not a valid choice)
Accumulator offset (unsigned 8-bit or 16-bit)
aa:00 = A
rr can specify X, Y, SP, or PC
Accumulator D offset indexed-indirect
rr can specify X, Y, SP, or PC
1 = 16-bit
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
Comments
Central Processor Unit (CPU)
Indexed Addressing Modes
Data Sheet
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