XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 198
XC912BC32CFU8
Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC912BC32CFU8.pdf
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Enhanced Capture Timer (ECT) Module
13.4.24 Pulse Accumulator B Flag Register
13.4.25 8-Bit Pulse Accumulators Holding Registers
Data Sheet
198
PBOVI — Pulse Accumulator B Overflow Interrupt Enable Bit
PBOVF — Pulse Accumulator B Overflow Flag
•
•
This bit is set when the 16-bit pulse accumulator B overflows from $FFFF to
$0000 or when 8-bit pulse accumulator 1 (PAC1) overflows from $FF to $00.
This bit is cleared by a write to the PBFLG register with bit 1 set. Any access to
the PACN1 and PACN0 registers will clear the PBOVF flag in this register when
TFFCA bit in register TSCR ($86) is set.
Address: $00B1
Address: $00B2
Address: $00B3
Address: $00B4
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
0 = Interrupt inhibited
1 = Interrupt requested if PBOVF is set
Figure 13-46. 8-Bit Pulse Accumulator Holding Register 3 (PA3H)
Figure 13-47. 8-Bit Pulse Accumulator Holding Register 2 (PA2H)
Figure 13-48. 8-Bit Pulse Accumulator Holding Register 1 (PA1H)
Read:Anytime
Write:Anytime
Figure 13-45. Pulse Accumulator B Flag Register (PBFLG)
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Enhanced Capture Timer (ECT) Module
0
0
0
0
0
Bit 6
Bit 6
Bit 6
6
0
0
6
0
6
0
6
0
Bit 5
Bit 5
Bit 5
5
0
0
5
0
5
0
5
0
Bit 4
Bit 4
Bit 4
4
0
0
4
0
4
0
4
0
Bit 3
Bit 3
Bit 3
3
0
0
3
0
3
0
3
0
M68HC12B Family — Rev. 8.0
Bit 2
Bit 2
Bit 2
2
0
0
2
0
2
0
2
0
PBOVF
Bit 1
Bit 1
Bit 1
1
0
1
0
1
0
1
0
MOTOROLA
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0
0
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