XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 217

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

14.3.5 SPI Register Descriptions
14.3.5.1 SPI Control Register 1
M68HC12B Family — Rev. 8.0
MOTOROLA
When SPE = 1
Bidirectional
SPC0 = 0
SPC0 = 1
Normal
Mode
Mode
SWOM enables open-drain output. PS4 becomes GPIO.
Control and data registers for the SPI subsystem are described in this section. The
memory address indicated for each register is the default address that is in use
after reset. The entire 512-byte register block can be mapped to any 2-Kbyte
boundary within the standard 64-Kbyte address space. For more information, refer
to
Read: Anytime
Write: Anytime
SPIE — SPI Interrupt Enable Bit
SPE — SPI System Enable Bit
Serial Out
Serial Out
Figure 14-14. Normal Mode and Bidirectional Mode
Section 5. Operating Modes and Resource
Serial In
Serial In
When MODF is set, SPE always reads 0. SP0CR1 must be written as part of a
mode fault recovery sequence.
SPI
SPI
Address:
Reset:
SWOM enables open-drain output.
Read:
Write:
0 = SPI interrupts are inhibited.
1 = Hardware interrupt sequence is requested each time the SPIF or MODF
0 = SPI internal hardware is initialized and SPI system is in a low-power
1 = PS4–PS7 are dedicated to the SPI function.
status flag is set.
disabled state.
Master Mode
MSTR = 1
$00D0
DDS5
DDS5
SPIE
Bit 7
0
Figure 14-15. SPI Control Register 1 (SP0CR1)
SPE
6
0
Serial Interface
MOMI
PS4
MO
MI
SWOM
5
0
MSTR
SWOM enables open-drain output. PS5 becomes GPIO.
4
0
Serial Out
Serial Out
Serial In
Serial In
SPI
SPI
SWOM enables open-drain output.
CPOL
Mapping.
3
0
Slave Mode
Serial Peripheral Interface (SPI)
MSTR = 0
DDS4
DDS4
CPHA
2
1
SSOE
Serial Interface
1
0
SISO
PS5
SO
SI
Data Sheet
LSBF
Bit 0
0
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