XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 71

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

4.4 Latching of Interrupts
M68HC12B Family — Rev. 8.0
MOTOROLA
$FFDC, $FFDD
$FFEC, $FFED
$FFDE, $FFDF
$FFDA, $FFDB
$FFCA–$FFCF
$FFFC, $FFFD
$FFEE, $FFEF
$FFEA, $FFEB
$FFFE, $FFFF
$FFFA, $FFFB
$FFD8, $FFD9
$FFD6, $FFD7
$FFD4, $FFD5
$FFD2, $FFD3
$FFD0, $FFD1
$FFC8–$FFC9
$FFC6, $FFC7
$FFC4, $FFC5
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FF80, $FFC3
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
Address
Vector
Reset
COP clock monitor fail reset
COP failure reset
Unimplemented instruction trap
SWI
XIRQ
IRQ
Real-time interrupt
Timer channel 0
Timer channel 1
Timer channel 2
Timer channel 3
Timer channel 4
Timer channel 5
Timer channel 6
Timer channel 7
Timer overflow
Pulse accumulator overflow
Pulse accumulator input edge
SPI serial transfer complete
SCI 0
Reserved
ATD
MSCAN wakeup
Reserved (not implemented)
MSCAN errors
MSCAN receive
MSCAN transmit
Reserved (implemented)
XIRQ is always level triggered and IRQ can be selected as a level-triggered
interrupt. These level-triggered interrupt pins should be released only during the
appropriate interrupt service routine. Generally, the interrupt service routine will
handshake with the interrupting logic to release the pin. In this way, the MCU will
Interrupt Source
Table 4-2. MC68HC(9)12BC32 Interrupt Vector Map
Resets and Interrupts
Mask
None
None
None
None
None
CCR
X bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
ATDCTL2
Register
COPCTL
SP0CR1
SC0CR2
RTICTL
TMSK1
TMSK1
TMSK1
TMSK1
TMSK1
TMSK1
TMSK1
TMSK1
TMSK2
CRIER
CRIER
CRIER
INTCR
PACTL
PACTL
CTCR
None
None
None
None
None
—
—
—
Local Enable
TIE, TCIE, RIE, ILIE
RWRNIE, TWRNIE,
COP rate selected
RERRIE, TERRIE,
BOFFIE, OVRIE
CME, FCME
TXEIE[2:0]
WUPIE
IRQEN
RXFIE
ASCIE
Bit(s)
PAOVI
None
None
None
None
SPIE
RTIE
C0I
C1I
C2I
C3I
C4I
C5I
PAI
C6I
C7I
TOI
—
—
—
Resets and Interrupts
Latching of Interrupts
to Highest I Bit
HPRIO Value
to Elevate
$CA–$CF
$80–$C3
$EC
$DE
$DC
$DA
$EE
$EA
$E2
$E0
$D8
$D6
$D4
$D2
$D0
$C8
$C6
$C4
$F2
$F0
$E8
$E6
$E4
Data Sheet
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