XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 289

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XC912BC32CFU8

Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
16.12.5 msCAN12 Receiver Flag Register
M68HC12B Family — Rev. 8.0
MOTOROLA
NOTE:
The bit time is determined by the oscillator frequency, the baud rate prescaler, and
the number of time quanta (Tq) clock cycles per bit (as shown in
The CBTR1 register can be written only if the SFTRES bit in CMCR0 is set.
All bits of this register are read and clear only. A flag can be cleared by writing a 1
to the corresponding bit position. A flag can be cleared only when the condition
which caused the setting is valid no longer. Writing a 0 has no effect on the flag
setting. Every flag has an associated interrupt enable flag in the CRIER register. A
hard or soft reset will clear the register.
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as
shown in
Address: $0104
Reset:
Read:
Write:
TSEG13
Figure 16-20. msCAN12 Receiver Flag Register (CRFLG)
WUPIF
Table
Bit 7
0
0
0
0
1
.
0
BitTime
16-8.
RWRNIF
msCAN12 Controller
TSEG12
TSEG22
6
0
=
Table 16-8. Time Segment Values
0
0
0
0
1
0
0
1
.
.
Presc
-------------------------------------- - number
f
CGMCANCLK
TWRNIF
Þ
5
0
TSEG11
TSEG21
value
0
0
1
1
1
0
0
1
.
.
RERRIF
4
0
Programmer’s Model of Control Registers
TSEG20
TSEG10
0
1
0
1
1
0
1
1
TERRIF
.
.
Þ
3
0
of
Þ
TimeQuanta
BOFFIF
16 Tq clock cycles
Time Segment 1
Time Segment 2
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
2 Tq clock cycles
8 Tq clock cycles
1 Tq clock cycle
1 Tq clock cycle
2
0
msCAN12 Controller
.
.
Table
OVRIF
1
0
16-8).
Data Sheet
Bit 0
RXF
0
289

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