SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 17

• Manufacturer Part Number: SPC8104
• Description: VGA LCD CONTROLLER
• Manufacturer: S-MOS Systems

Key
CPU Interface
SPC8104
A
I
O
I/O = Bidirectional
P
Pin Name
A[0:16],
LA[17:23]
D[0:15]
ALE
MEMEN
IOR#
IOW#
MEMR#
MEMW#
IOEN#
READY
RESET
IRQ
MEMCS16#
IOCS16#
BHE#
RDACK#
PIN DESCRIPTION
412-1.0
= Analog
= Input
= Output
= Power
Type Pin #
I
I/O
I
I
I
I
I
I
I
O
I
O
O
O
I
O
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
100~106,
109~116,
119~127
2~10,
13~19
99
92
94
93
91
90
95
89
84
83
87
88
98
20
Description
CPU bus unlatched address inputs. For an 8-bit CPU interface configuration,
LA[20:23] are ignored and LA[17:19] should be connected to the latched CPU
address SA[17:19]. In Suspend Mode, the Address inputs are internally masked off.
16 bit ISA-Bus data bus. These lines are driven by the chip only during read cycles,
and are in a hi-Z state at all other times. In Suspend Mode, these inputs are
internally masked off.
ISA Bus Address Latch Enable. ALE is ignored for an 8-bit CPU interface
configuration. In Suspend Mode the this input is disabled.
ISA Bus Memory Enable. This signal should be connected to the -REFRESH signal
on the ISA bus. When this signal is low (e.g. during a system memory refresh
cycle), memory address decoding is disabled.
ISA Bus I/O Read Strobe. In Suspend Mode the this input is disabled.
ISA Bus I/O Write Strobe. In Suspend Mode the this input is disabled.
ISA Bus Memory Read Strobe. In Suspend Mode the this input is disabled.
ISA Bus Memory Write Strobe. In Suspend Mode the this input is disabled.
ISA Bus I/O Enable. This input should be connected to the ISA bus AEN signal.
When this signal is high, I/O address decoding is disabled. In Suspend Mode the
this input is disabled.
ISA Bus READY signal. This output is driven low to force the CPU to insert wait
states during memory cycles. READY is released to high-Z after a transfer is
complete.
The active high Reset signal from the CPU clears all internal registers and forces all
signals to their inactive state. During Suspend Mode the RESET input is ignored.
ISA Bus Vertical Interrupt. When enabled, a Vertical Retrace Interrupt will cause
this signal to be driven from a logic 0 state to a logic 1 (rising-edge triggered
interrupt). Once set, this interrupt must be cleared by a bit in the CRTC registers. A
control bit in the Auxiliary Registers allows this output to be optionally disabled (tri-
stated).
ISA Bus Memory Chip Select 16. Address inputs LA[23:17] are decoded to drive
this output low when a valid memory address (AXXXXh, BXXXXh) appears on the
bus.
ISA Bus I/O chip Select 16. Address inputs A[15:0] and IOEN# are decoded to drive
this output low when a valid SPC8104 I/O register address appears on the bus.
Note that I/O addresses 3C6h-3C9h does not result in IOCS16# being driven low
(i.e. internal LUT register reads and writes are 8 bit cycles).
ISA Bus Byte High Enable. In Suspend Mode the this input is disabled.
Read Acknowledge. This pin goes low during valid I/O or memory reads to the chip.
Data Sheet
DS-11