SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 88

• Manufacturer Part Number: SPC8104
• Description: VGA LCD CONTROLLER
• Manufacturer: S-MOS Systems

bit 7
bit 6
bit 5
bit 4
bits 3-2
bit 1
bit 0
bit 4
Hardware Functional Specification
03 Power Save Register RW
Doze Mode
Enable
04 Clock Control Register RW
SP1-62
n/a
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Doze Mode
2 Select
Doze Mode Enable
The Doze Mode Enable bit is used to enable Doze mode, the function of which is determined by
the Doze Mode 1 and 2 Select bits. If the SUSPEND# input pin is low or the Suspend Mode Enable
bit set, then this bit is ignored.
Doze Mode 2 Select
The Doze Mode 2 Select bit enables Doze mode 2 function when the Doze Mode Enable bit is set
or when the DOZE# input pin is low. Seesection 10.1 on page 48, for details.
Doze Mode 1 Select
The Doze Mode 2 Select bit enables Doze mode 1 function when the Doze Mode Enable bit is set
or when the DOZE# input pin is low. See section 10.1 on page 48, for details.
CLKI Disable
The CLKI Disable bit is intended to be used in Suspend mode with MEMEN, self-refresh, or
PDCLK DRAM refresh clock source option selected (via AUX[02] bit 3, 2). When this bit is 1, CLKI
clock source is masked off. When this bit is 0, CLKI clock source is enabled. Note that this bit
should never to be set in Active mode or Doze mode.
Doze Mode 2 Clock Divide Bits [1:0]
These bits select the amount of clock divide of CLKI, as described in the following table, during the
power down state of Doze mode 2. These bits have no effect outside Doze mode 2. Note that the
clock divide here applies to the CLKI source that may have been affected by Clock Control register
bits.
Suspend Mode Enable
The Suspend Mode Enable bit is used to enable Software Suspend mode. If the SUSPEND# input
pin is low, then this bit is ignored. See section 10.1 on page 48, for details.
LCD Power Disable
Setting this bit to 1 forces the LCDPWR# output pin high so that panel power can be turned off.
Sequencer Scaling
The Sequencer Scaling bit is used to better support small passive single panels that typically
require lower frame rate. When this bit is set, the Sequencer and the pixel output data path are run-
ning at half the normal rate so that panel frame rate is effectively halved.
n/a
Doze Mode 2 Clock
Divide Bit 1
Doze Mode
1 Select
0
0
1
1
n/a
Table 0-34 Doze Mode 2 Clock Division
CLKI
Disable
Sequencer
Scaling
Doze Mode 2 Clock
Divide Bit 0
X15-SP-001-08.1
0
1
0
1
bit 1
Doze Mode 2 Clock Divide
n/a
CLKI Clock Divide
bit 0
1 (no divide)
n/a
Factor
2
4
8
Suspend
Mode
Enable
n/a
LCD Power
Disable
412-1.0
SPC8104
n/a