SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 42

• Manufacturer Part Number: SPC8104
• Description: VGA LCD CONTROLLER
• Manufacturer: S-MOS Systems

Hardware Functional Specification
Pin Name
RESET
IRQ
MEMCS16#
IOCS16#
BHE#
RDACK#
Pin Name
MA[0:9]
MD[0:4]
MD[7:15]
MD[5:6]
RAS#
LCAS#
(LWE#)
UCAS#
(CAS#)
WE#
(UWE#)
SP1-16
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Type Pin #
O
I/O
I/O
O
O
O
O
Type Pin #
I
O
O
O
I
O
48, 46,
42, 40,
39, 41,
45, 47,
49, 50
74, 72,
70, 68,
66, 58,
57, 59,
61, 63,
67, 69,
71, 73
62, 60
51
56
52
53
84
83
87
88
98
20
Drive
CO1
C/
TS1U
C/TS1
CO2
CO2
CO2
CO2
Drive
CS
TS1
TS2
TS2
C
CO1
Table 0-2 Video Memory Interface
Description
Multiplexed row/column address bits for video display memory.
Data bits for video display memory. The output drivers of these pins are
placed into a high-impedance state when RESET is high. On the falling
edge of RESET, the values on MD[3:0] are latched into a read-only
Auxiliary Register and are available to be read as configuration inputs.
Also, the values on MD[5:6] are used to configure other various
hardware options - see section 5.4 on page 21, for details. Note that
there are internal pullup resistors on the inputs of these pins except
MD[5:6].
DRAM Row Address Strobe.
DRAM Column Address Strobe for low byte (LCAS#), or Write Enable
Strobe for low byte (LWE#), as determined by logic value on MD[6]
during RESET (see pin mapping table).
DRAM Column Address Strobe for high byte (UCAS#), or single Column
Address Strobe (CAS#), as determined by logic value on MD[6] during
RESET (see pin mapping table).
DRAM Write Enable Strobe (WE#), or Write Enable Strobe for high byte
(UWE#), as determined by logic value on MD[6] during RESET (see pin
mapping table).
Table 0-1 CPU Interface
The active high Reset signal from the CPU clears all internal
registers and forces all signals to their inactive state. During
Hardware Suspend Mode the RESET input is ignored.
ISA Bus Vertical Interrupt. When enabled, a Vertical Retrace
Interrupt will cause this signal to be driven from a logic 0 state to a
logic 1 (rising-edge triggered interrupt). Once set, this interrupt must
be cleared by a bit in the CRTC registers. A control bit in the
Auxiliary Registers allows this output to be optionally disabled (tri-
stated).
ISA Bus Memory Chip Select 16. Address inputs LA[23:17] are
decoded to drive this output low when a valid memory address
(AXXXXh, BXXXXh) appears on the bus.
ISA Bus I/O chip Select 16. Address inputs A[15:0] and IOEN# are
decoded to drive this output low when a valid SPC8104 I/O register
address appears on the bus. Note that I/O addresses 3C6h-3C9h
does not result in IOCS16# being driven low (i.e. internal LUT
register reads and writes are 8 bit cycles).
ISA Bus Byte High Enable.
Read Acknowledge. This pin goes low during valid I/O or memory
reads to the chip.
Description
X15-SP-001-08.1
412-1.0
SPC8104