SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 51

• Manufacturer Part Number: SPC8104
• Description: VGA LCD CONTROLLER
• Manufacturer: S-MOS Systems

7.1
SPC8104
Symbol
t10a
t10b
t11a
t11b
412-1.0
t2a
t2b
t3a
t3b
t6a
t6b
t8a
t8b
t8c
t1
t4
t5
t7
t9
SPC8104 outputs
CPU Bus Cycle Timing - 8-bit Memory and I/O
ISA bus outputs
A[19:17] valid setup to ALE negated (falling edge)
A[19:0], MEMEN valid before MEMR#, MEMW# asserted
A[15:0], IOEN# valid before IOR#, IOW# asserted
A[19:0], MEMEN hold from MEMR#, MEMW# negated
A[15:0], IOEN# hold from IOR#, IOW negated
MEMW# asserted to D[7:0] valid
D[7:0] setup to IOW# negated
D[7:0] hold from MEMW# negated
D[7:0] hold from IOW# negated
MEMR#, MEMW# asserted to READY negated
READY negated pulse width (dual panel)
READY negated pulse width (single panel)
IOR# asserted to D[7:0] valid
READY asserted to D[7:0] valid (read)
D[7:0] hold from MEMR# negated
D[7:0] hold from IOR# negated
MEMR# negated to D[7:0] hi-Z delay
IOR# negated to D[7:0] hi-Z delay
MEMR#,MEMW#,
A[19:0],MEMEN,
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Figure 4 : CPU Bus Cycle Timing - 8-bit Memory and
IOR#,IOW#
READY
IOEN#
(write)
D[7:0]
D[7:0]
(read)
ALE
Table 0-19 CPU Bus Cycle Timing - 8-bit Memory and I/O
Hi-Z
Parameter
t1
t2
t7
X15-SP-001-08.1
t4
t8
t5
write
t9
I/OSource: a000070.cdr
Min
10
24
10
10
10
0
0
0
0
0
read
Hardware Functional Specification
t10
t3
t6
Typ
t11
Max
36Ts
69Ts
3Ts
50
80
70
30
30
Units
SP1-25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns