SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 46

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SPC8104

Manufacturer Part Number
SPC8104
Description
VGA LCD CONTROLLER
Manufacturer
S-MOS Systems
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SPC8104F0A
Manufacturer:
EPSON
Quantity:
586
Hardware Functional Specification
Pin Name
PDCLK
SUSPEND#
DOZE#
Pin Name
V
V
V
V
V
V
Pin Name
TSTCO
TSTEN
N/C
SP1-20
DD
DD
DD
SS
SS
SS
CORE
I/O
CLKI
CORE
I/O
CLKI
S-MOS Systems, Inc. • Tel: (408) 922-0200 • Fax: (408) 922-0238 • http://www.smos.com
Type
I
I
Type
I
I
I
Type
P
P
P
P
P
P
Pin #
38
82
78
Pin #
79
80
81
Pin #
12, 33, 55, 97, 118 V
1, 22, 44, 65, 86,
108
76
11, 32, 54, 96, 117 V
21, 43, 64, 85,
107, 128
75
Drv
C
CS
CS
Drv
CD
CD
Table 0-9 Power Save Mode Control
Table 0-10 Power Supply
Table 0-11 Test Function
Description
Power Down Clock. This input may be used to provide a low
frequency clock for generating DRAM refresh in Suspend mode, as
an optional alternative to using the CLKI or MEMEN input as the
DRAM refresh clock source. This clock input should be driven by a 32
kHz 50% duty cycle clock. The PDCLK input is used to directly
generate the RAS and CAS pulses in Suspend mode.
Refer to section 10.3 on page 52, for details.
A low level on this pin puts the chip into the Hardware Suspend
mode. The SUSPEND# signal overrides any software initiated power
save modes as well as the DOZE# input pin, and disables the CPU
bus interface inputs. CPU Address and Data inputs are masked when
this signal is low. When in Suspend Mode the UD[3:0], LD[3:0],
XSCL, LP, YD and WF signals are driven into a low state (or
optionally, a high impedance state) and the LCDPWR# signal is
driven high.
A low level on this pin puts the chip into Doze mode. The function of
the Doze mode is determined by the Doze Mode Select bits in
AUX[03]. This pin is ignored if the SUSPEND# input pin is asserted.
Description
This pin enables the chip’s test mode for the core logic. This pin must
always be unconnected or tied to ground.
This pin enables the chip’s test mode for the I/O cells. This pin must
always be unconnected or tied to ground.
No Connection
Description
V
V
V
V
DD
DD
DD
SS
SS
SS
supply for core logic.
supply for I/O pins.
supply for CLKI pin.
supply for core logic.
supply for I/O pins.
supply for CLKI pin.
X15-SP-001-08.1
412-1.0
SPC8104

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