SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 78

• Manufacturer Part Number: SPC8104
• Description: VGA LCD CONTROLLER
• Manufacturer: S-MOS Systems

10.3 Implementation Notes
Hardware Functional Specification
SP1-52
1. For Software Suspend Mode and Hardware Suspend Mode using the MEMEN input as the refresh clock
2. For Software Suspend Mode and Hardware Suspend Mode using the PDCLK input as the refresh clock
3. The self-refresh mode option (AUX[02] bit 3-2 = 10b) available in Software Suspend Mode and Hardware
4. In Software Suspend Mode, software may set an Auxiliary Register bit to mask off the CLKI clock input. This
5. In Hardware Suspend Mode, the CLKI clock input is automatically masked off by hardware if the self-refresh
6. In Hardware Suspend Mode, if MEMEN is selected as the refresh clock source, then the CLKI clock input is
7. In Hardware Suspend Mode, if PDCLK is selected as the refresh clock source, then the CLKI clock input is
8. In Hardware Suspend Mode, if the CLKI clock input is used as the refresh clock source, then CLKI cannot be
9. The output pin LCDPWR# should be used to control the LCD panel's power supply via external circuitry.
10. After RESET is asserted, LCDPWR# is held high until the CRTC is programmed and running (i.e. LCD inter-
11. Circuitry in the chip will ensure that upon entering Suspend Mode, LCDPWR# will be driven high (panel pow-
12. If the Sequencer is stopped, (Sequencer Reset Register bit 1 or bit 0 = 0), then LCDPWR# will be driven high
13. Power up configuration pin MD[5] allows selecting the Suspend mode state of the LCD interface signals. In
source (AUX[02] bit 3-2 = 01b, the clock source from MEMEN should be running at a frequency of 64 kHz.
MEMEN’s active low pulse width should be as short as possible (but 50 ns greater than the min. DRAM RAS
pulse width requirement). The use of a 64 kHz clock source is required for meeting the 256 cycles/4 msec
DRAM refresh specification. Normally MEMEN is connected to the ISA bus signal -REFRESH, a 64 KHz
clock with an active low period ~ 500 ns. The 64 kHz input can be internally divided down to 8 kHz by setting
the 32/4msecRefresh Select bit (AUX[02] bit 0 = 1).
source (AUX[02] bit 3-2 = 11b, the clock source connected to the PDCLK input should be a 32 kHz 50% duty
cycle clock. This 32 kHz clock input is doubled internally to a generate a 64 kHz clock source which provides
the appropriate duty cycle and active period, as required by the 64 kHz refresh rate for 256cycles/4ms
DRAM. The internal 64 kHz refresh rate can further be internally divided down to 8 kHz to support 256cycle/
32msec DRAM by setting the 32/4msec Refresh Select bit (AUX[02] bit 0 = 1).
Suspend Mode must only be enabled if the DRAM installed supports self-refresh operation.
can be used to further reduce system power consumption.
option is enabled.
automatically masked off by hardware.
automatically masked off by hardware.
masked off by hardware.
When LCDPWR# is high, the external panel power supply should be turned off. When LCDPWR# is low, the
power supply should be enabled.
face signals are active).
er shut off) before the interface signals are tri-stated or forced low. Upon exiting Suspend Mode, LCDPWR#
will be driven low (panel power turned on) after the interface signals are returned to their active driving
states. This sequencing of the LCDPWR# and interface signals is done to protect the panel from being dam-
aged from DC signals applied to the interface while it is powered up.
(panel power shut off) before the Sequencer is shut down and the LCD interface signals are halted. Upon re-
starting the Sequencer (by setting Sequencer Reset Register bit 1 and bit 0 to 1), LCDPWR# will be driven
low (panel power turned on) after the Sequencer is has started running and the LCD interface signals are re-
turned to their active driving states. This sequencing of the LCDPWR# and interface signals is done to pro-
tect the panel from being damaged from DC signals applied to the interface while the Sequencer is stopped
and all chip output signals are inactive.
Suspend mode, the LCD interface signals can all be driven low, or can be put into a high-impedance state,
as selected by this option.
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
X15-SP-001-08.1
412-1.0
SPC8104