SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 41

• Manufacturer Part Number: SPC8104
• Description: VGA LCD CONTROLLER
• Manufacturer: S-MOS Systems

5.0
Key
SPC8104
Pin Name
A[0:16],
LA[17:23]
D[0:15]
ALE
MEMEN
IOR#
IOW#
MEMR#
MEMW#
IOEN#
READY
All signal and pin names followed by # are active low (e.g., MEMR# would be read as MEMR).
412-1.0
C
CD
CS
COx
TSx
TSxU
PIN DESCRIPTIONS
Type Pin #
I
I/O
I
I
I
I
I
I
I
O
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
=
=
=
=
=
=
100~106,
109~116,
119~127
2~10,
13~19
99
92
94
93
91
90
95
89
CMOS level input
CMOS level input with 90 k0 k
CMOS level input with hysteresis
CMOS level output, x denotes output driver type - see DC characteristics for
rating.
Tri-state CMOS level driver, x denotes driver type - see DC characteristics for
rating.
Tri-state CMOS level driver with 90 k
see DC characteristics for rating.
Drive
C
C/TS1 16 bit ISA-Bus data bus. These lines are driven by the chip only
C
CS
CS
CS
CS
CS
CS
TS2
Table 0-1 CPU Interface
Description
CPU bus unlatched address inputs. For an 8-bit CPU interface
configuration, LA[20:23] should be connected to ground and
LA[17:19] should be connected to the latched CPU address
SA[17:19]. In Hardware Suspend Mode, the Address inputs are
internally masked off.
during read cycles, and are in a hi-Z state at all other times. In
Hardware Suspend Mode, these inputs are internally masked off.
ISA Bus Address Latch Enable. ALE should be connected to V
for an 8-bit CPU interface configuration.
ISA Bus Memory Enable. This signal should be connected to the
-REFRESH signal on the ISA bus. When this signal is low (e.g.
during a system memory refresh cycle), memory address decoding
is disabled.
ISA Bus I/O Read Strobe. In Hardware Suspend Mode the this input
is disabled.
ISA Bus I/O Write Strobe. In Hardware Suspend Mode the this input
is disabled.
ISA Bus Memory Read Strobe. In Suspend Mode the this input is
disabled.
ISA Bus Memory Write Strobe. In Suspend Mode the this input is
disabled.
ISA Bus I/O Enable. This input should be connected to the ISA bus
AEN signal. When this signal is high, I/O address decoding is
disabled. In Hardware Suspend Mode the this input is disabled.
ISA Bus READY signal. This output is driven low to force the CPU to
insert wait states during memory cycles. READY is released to high-
Z after a transfer is complete.
X15-SP-001-08.1
pull down resistor.
pull up resistor, x denotes driver type -
Hardware Functional Specification
DD
SP1-15
I/O