SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 85

• Manufacturer Part Number: SPC8104
• Description: VGA LCD CONTROLLER
• Manufacturer: S-MOS Systems

11.3 I/O Register Summary
This section summarizes the I/O registers of SPC8104 - only those register bits supported by the
chip are shown. Note that the functionality of a subset of the IBM VGA standard registers is sup-
ported, with an additional set of Auxiliary Registers containing SPC8104 specific functions. Only
details of the register functions which are not part of the VGA standard definition are given below.
Auxiliary Registers;
bit 7
bit 6
bit 5
bit 4
bit 2
bit 0
SPC8104
Auxiliary Index/Data Register
3DEh RW
n/a
00 Extended Function Register 0 RW
16/8 Bit CPU
I/O Select
01 Output Preference Register RW
n/a
Unless otherwise noted, all read/write register bits are cleared to 0 after a RESET.
All register bits marked as “n/a” are undefined. There is no effect if they are written to, and
reading these bits will return an undefined value.
412-1.0
3DFh RW
n/a
16/8 Bit CPU
Memory
Select
Graphics
VExpand
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16/8 Bit CPU I/O Select
When this bit is set to 0, CPU I/O transfer is 8-bit only. When this bit set to 1, CPU I/O transfer can
be 8-bit or 16-bit.
16/8 Bit CPU Memory Select
When this bit is set to 0, CPU memory transfer is 8-bit only. When this bit set to 1, CPU memory
transfer can be 8-bit or 16-bit.
LUT Read Disable
When this bit is set to 0, I/O reads to the LUT registers are allowed. When this bit is set to 1, I/O
reads to the LUT registers are disabled.
3C9h Write Disable
When this bit is set to 0, I/O writes to the LUT Data register (3C9h) is allowed. When this bit is set
to 1, I/O writes to the LUT Data register (3C9h) is disabled.
IRQ Output Enable
When this bit is set to 0, the IRQ output is held in a high impedance state. When this bit is set to 1,
the IRQ output pin is enabled and will be driven to indicate the Vertical Retrace interrupt status.
LCD B Registers Program Enable
This bit is used to access the hidden CRTC B Set Data Registers. When this bit is set to 0,
accesses to CRTC register with index 01h, 05h, 10h, and 12h affect the normal CRTC registers.
When this bit is set to 1, then the “B set” CRTC registers are enabled, and accesses to CRTC reg-
ister with index 01h, 05h, 10h, and 12h affect the corresponding “B set” CRTC registers.
n/a
Text
VExpand
LUT Read
Disable
n/a
Green Only/
NTSC GS
Weighting
3C9h Write
Disable
X15-SP-001-08.1
Auxiliary
Index
bit 3
Graphics
Reverse
n/a
Auxiliary
Index
bit 2
Text
Reverse
IRQ Output
Enable
Hardware Functional Specification
Auxiliary
Index
bit 1
Auto-Center
Enable
n/a
Auxiliary
Index
bit 0
Slow Blink
Select
LCD B Reg
Program
Enable
SP1-59