SPC8104 S-MOS Systems, SPC8104 Datasheet - Page 94

• Manufacturer Part Number: SPC8104
• Description: VGA LCD CONTROLLER
• Manufacturer: S-MOS Systems

Sequencer Registers
Hardware Functional Specification
Sequencer Index/Data Register
3C4h RW
n/a
00 Reset Register RW
n/a
01 Clocking Mode Register RW
n/a
02 Map Mask Register RW
n/a
03 Character Map Select Register RW
n/a
04 Memory Mode Register RW
n/a
SP1-68
index 01 Clocking Mode Register bits 4, 2, 1, 0 - are read/write bits that have no effect in hard-
ware. These bits are provided for compatibility with some software that expects to read or write
these bits.
index 00 bits 1, 0 Sequencer Reset bits - setting either or both of these bits to 0 will stop (i.e.
reset) the Sequencer. Because stopping the Sequencer halts all interface signals to the LCD
panel, logic exists to shut down the panel power (LCDPWR# goes high) before the Sequencer is
actually shut down. During this delay between reset request (i.e. setting the reset bits) and
actual Sequencer halting, any in-progress memory accesses will be completed. Also, during the
actual period that the Sequencer is held in a reset state, if a memory access request is issued by
the system, it will be held pending the restart of the Sequencer (while the memory cycle is held
pending, the READY output is held low).
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
3C5h RW
n/a
n/a
n/a
n/a
n/a
n/a
Select
bit 2
n/a
n/a
Screen Off
n/a
Map A
n/a
n/a
n/a
Dummy
Shift by 4
(see note)
n/a
Map B
Select
bit 2
n/a
X15-SP-001-08.1
n/a
n/a
Dotclock
Divide by 2
Plane 3
Write Enable
Map A
Select
bit 1
Chain 4
n/a
Dummy
Shift Load
(see note)
Plane 2
Write Enable
Map A
Select
bit 0
Odd/Even
Map Select
bit 2
Sequencer Index
bit 1
Sequencer
Reset
Dummy
Bandwidth
(see note)
Plane 1
Write Enable
Map B
Select
bit 1
RO Status
Read as 1
bit 0
Sequencer
Reset
Dummy
8/9 Dot
Select
(see note)
Plane 0
Write Enable
Map B
Select
bit 0
n/a
412-1.0
SPC8104