ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 107

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Note 1:
Note 2:
9.3
Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status,
framer interrupt status, IBO configuration, MCLK configuration, and BPCLK configuration. The global registers bit
descriptions are presented in this section.
Table 9-10. Global Register Set
ADDRESS
0FCh
0FDh
0FAh
0FBh
0FEh
0F0h
0F1h
0F2h
0F3h
0F4h
0F5h
0F6h
0F7h
0F8h
0F9h
01Fh
Global Register Definitions
Reserved registers should only be written with all zeros.
The global registers are located in the framer address space. The corresponding address space for the other seven framers is
“Reserved,” and should be initialized with all zeros for proper operation.
GTCCR
GFSRR
GTCR1
GTCR2
GLSRR
GBIMR
GFIMR
GLIMR
GFISR
GBISR
NAME
GLISR
GFCR
IDR
—
—
—
Global Transceiver Control Register 1
Global Framer Control Register
Global Transceiver Control Register 2
Global Transceiver Clock Control Register
Reserved
Global LIU Software Reset Register
Global Framer and BERT Software Reset Register
Reserved
Device Identification Register
Global Framer Interrupt Status Register
Global BERT Interrupt Status Register
Global LIU Interrupt Status Register
Global Framers Interrupt Mask Register
Global BERT Interrupt Mask Register
Global LIU Interrupt Mask Register
Reserved
107 of 273
DESCRIPTION
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
R
R
R
R