ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 143

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: This register has an alternate definition for T1 mode. See
Bit 6: Receive HDB3 Enable (RHDB3).
Bit 5: Receive-Signaling Mode Select (RSIGM).
Bit 4: Receive G.802 Enable (RG802). See
Bit 3: Receive CRC-4 Enable (RCRC4).
Bit 2: Frame Resync Criteria (FRC).
Bit 1: Sync Enable (SYNCE).
Bit 0: Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive-side framer is
initiated. Must be cleared and set again for a subsequent resync.
0 = HDB3 disabled
1 = HDB3 enabled (decoded per O.162)
0 = CAS signaling mode
1 = CCS signaling mode
0 = do not force RCHBLK high during bit 1 of time slot 26
1 = force RCHBLK high during bit 1 of time slot 26
0 = CRC-4 disabled
1 = CRC-4 enabled
0 = resync if FAS received in error three consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times
0 = auto resync enabled
1 = auto resync disabled
—
7
0
RCR1 (E1 Mode)
Receive Control Register 1
081h + (200h x n): where n = 0 to 3, for Ports 1 to 4
RHDB3
6
0
RSIGM
5
0
Figure 10-23
RCR1
143 of 273
RG802
0
4
.
for details.
RCRC4
3
0
FRC
2
0
SYNCE
1
0
RESYNC
0
0