ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 114

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: Channel 4 Framer and BERT Software Reset (FSRST4). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
Bit 2: Channel 3 Framer and BERT Software Reset (FSRST3). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
Bit 1: Channel 2 Framer and BERT Software Reset (FSRST2). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
Bit 0: Channel 1 Framer and BERT Software Reset (FSRST1). Framer logic and registers are reset with a 0-to-1
transition in this bit. The reset is released when a zero is written to this bit.
0 = Normal operation
1 = Reset framer and BERT
0 = Normal operation
1 = Reset framer and BERT
0 = Normal operation
1 = Reset framer and BERT
0 = Normal operation
1 = Reset framer and BERT
—
7
0
GFSRR
Global Framer and BERT Software Reset Register
0F6h
—
6
0
—
5
0
114 of 273
—
4
0
FSRST4
3
0
FSRST3
2
0
FSRST2
1
0
FSRST1
0
0