ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 154

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts.
Bit 7: Receive Remote Alarm Indication Condition Clear (RRAIC). Falling edge detect of RRAI. Set when a
RRAI condition has cleared.
Bit 6: Receive Alarm Indication Signal Condition Clear (RAISC). Falling edge detect of RAIS. Set when a RAIS
condition has cleared.
Bit 5: Receive Loss of Signal Condition Clear (RLOSC). Falling edge detect of RLOS. Set when an RLOS
condition has cleared.
Bit 4: Receive Loss of Frame Condition Clear (RLOFC). Falling edge detect of RLOF. Set when an RLOF
condition has cleared.
Bit 3: Receive Remote Alarm Indication Condition Detect (RRAID). Rising edge detect of RRAI. Set when a
remote alarm is received at RTIP and RRING.
Bit 2: Receive Alarm Indication Signal Condition Detect (RAISD). Rising edge detect of RAIS.Set when an
unframed all-ones code is received at RTIP and RRING.
Bit 1: Receive Loss of Signal Condition Detect (RLOSD). Rising edge detect of RLOS. Set when 192
consecutive zeros have been detected at RTIP and RRING.
Bit 0: Receive Loss of Frame Condition Detect (RLOFD). Rising edge detect of RLOF. Set when the DS26524
has lost synchronized to the received data stream.
RRAIC
7
0
RLS1
Receive Latched Status Register 1
090h + (200h x n): where n = 0 to 3, for Ports 1 to 4
RAISC
6
0
RLOSC
5
0
RLOFC
154 of 273
0
4
RRAID
3
0
RAISD
2
0
RLOSD
1
0
RLOFD
0
0