ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 122
ds26524
Manufacturer Part Number
ds26524
Description
Ds26524 Quad T1/e1/j1 Transceiver
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS26524.pdf
(273 pages)
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9.4
See
9.4.1
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive CRC-16 Display (RCRCD).
Bit 6: Receive HDLC Reset (RHR). Will reset the receive HDLC controller and flush the receive FIFO. Note that
this bit is a acknowledged reset. The host should set this bit and the DS26524 will clear it once the reset operation
is complete. The DS26524 will complete the HDLC reset within two frames.
Bit 5: Receive HDLC Mapping Select (RHMS).
Bit 4 to 0: Receive HDLC Channel Select 4 to 0 (RHCS[4:0]). These bits determine which DS0 is mapped to the
HDLC controller when enabled with RHMS = 0. RHCS[4:0] = all 0s selects channel 1, RHCS[4:0] = all 1s selects
channel 32 (E1). A change to the receive HDLC channel select is acknowledged only after a receive HDLC reset
(RHR).
Table 9-3
Framer Register Definitions
Receive Register Definitions
0 = Do not write received CRC-16 code to FIFO (default)
1 = Write received CRC-16 code to FIFO after last octet of packet
0 = Normal operation
1 = Reset receive HDLC controller and flush the receive FIFO
0 = Receive HDLC assigned to channels
1 = Receive HDLC assigned to FDL (T1 mode), Sa bits (E1 mode)
RCRCD
for the complete framer register list.
7
0
RHC
Receive HDLC Control Register
010h + (200h x n): where n = 0 to 3, for Ports 1 to 4
RHR
6
0
RHMS
5
0
RHCS4
122 of 273
0
4
RHCS3
3
0
RHCS2
2
0
RHCS1
1
0
RHCS0
0
0
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