ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 152

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 2 to 0: Receive Spare Code Length Definition Bits (RSC[2:0]).
Bit #
Name
Default
Bit 2: Receive BERT Port Direction Control (RBPDIR).
Bit 1: Receive BERT Port Framed/Unframed Select (RBPFUS) (T1 Mode Only).
Bit 0: Receive BERT Port Enable (RBPEN).
RSC2
0
0
0
0
1
1
1
1
0 = Normal (line) operation. Receive BERT port receives data from the receive framer.
1 = System (backplane) operation. Receive BERT port receives data from the transmit path. The transmit
path enters the receive BERT on the line side of the elastic store (if enabled).
0 = The receive BERT will not clock data from the F-bit position (framed).
1 = The receive BERT will clock data from the F-bit position (unframed).
0 = Receive BERT port is not active.
1 = Receive BERT port is active.
RSC1
—
—
—
0
7
0
7
0
0
1
1
0
0
1
1
T1RSCC (T1 Mode Only)
In-Band Receive Spare Control Register
089h + (200h x n): where n = 0 to 3, for Ports 1 to 4
RXPC
Receive Expansion Port Control Register
08Ah + (200h x n): where n = 0 to 3, for Ports 1 to 4
RSC0
—
—
—
0
1
0
1
0
1
0
1
6
0
6
0
LENGTH SELECTED
—
—
—
5
0
5
0
(BITS)
8:16
1
2
3
4
5
6
7
152 of 273
—
—
4
0
—
0
4
—
—
3
0
—
3
0
RBPDIR
RBPDIR
RSC2
2
0
2
0
RBPFUS
RSC1
—
1
0
1
0
RBPEN
RBPEN
RSC0
0
0
0
0