ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 169

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 5: Receive FIFO Overrun (ROVR).
Bit 4: Receive HDLC Opening Byte Event (RHOBT).
Bit 3: Receive Packet-End Event (RPE).
Bit 2: Receive Packet-Start Event (RPS).
Bit 1: Receive FIFO Above High Watermark Set Event (RHWMS).
Bit 0: Receive FIFO Not Empty Set Event (RNES).
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
—
7
0
RIM5
Receive Interrupt Mask Register 5 (HDLC)
0A4h + (200h x n): where n = 0 to 3, for Ports 1 to 4
—
6
0
ROVR
5
0
RHOBT
169 of 273
0
4
RPE
3
0
RPS
2
0
RHWMS
1
0
RNES
0
0