ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 225
ds26524
Manufacturer Part Number
ds26524
Description
Ds26524 Quad T1/e1/j1 Transceiver
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS26524.pdf
(273 pages)
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9.6
Table 9-21. BERT Register Set
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Alternating Word Count Rate Bits 7 to 0 (ACNT[7:0]). When the BERT is programmed in the
alternating word mode, the words will repeat for the count loaded into this register, then flip to the other word and
again repeat for the number of times loaded into this register. ACNT0 is the LSB of the 8-bit alternating word count
rate counter.
110Ch
110Dh
ADDR
110Ah
110Bh
110Eh
110Fh
1100h
1101h
1102h
1103h
1104h
1105h
1106h
1107h
1108h
1109h
BERT Register Definitions
ACNT7
7
0
BAWC
NAME
BRP1
BRP2
BRP3
BRP4
BBC1
BBC2
BBC3
BBC4
BEC1
BEC2
BEC3
BLSR
BSIM
BC1
BC2
ACNT6
BAWC
BERT Alternating Word Count Rate Register
1100h + (10h x n): where n = 0 to 3, for Ports 1 to 4
BERT Alternating Word Count Rate Register
BERT Repetitive Pattern Set Register 1
BERT Repetitive Pattern Set Register 2
BERT Repetitive Pattern Set Register 3
BERT Repetitive Pattern Set Register 4
BERT Control Register 1
BERT Control Register 2
BERT Bit Count Register 1
BERT Bit Count Register 2
BERT Bit Count Register 3
BERT Bit Count Register 4
BERT Error Count Register 1
BERT Error Count Register 2
BERT Error Count Register 3
BERT Latched Status Register
BERT Status Interrupt Mask Register
6
0
ACNT5
5
0
ACNT4
225 of 273
4
0
DESCRIPTION
ACNT3
3
0
ACNT2
2
0
ACNT1
1
0
ACNT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
R
R
R
R
R
R
R
R
R
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