ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 108

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name
Register Description:
Register Address:
Bit #
Name
Default
Bit 5: Receive Loss of Frame/Loss of Transmit Clock Indication Select (RLOFLTS).
Bit 4: Global IBO Enable (GIBO). This bit is used to select either the internal mux for IBO operation or an external
wire-OR operation. Normally this bit should be set = 0 and the internal mux used.
Bit 2: Bulk Write Enable (BWE). When this bit is set, a port write to one of the quad ports is mapped into all four
ports. This applies to the framer, BERT, and LIU register sets. It must be cleared before performing a read
operation. This bit is useful for device initialization.
Bit 1: Global Counter Latch Enable (GCLE). A low-to-high transition on this bit will, when enabled, latch the
framer performance monitor counters. Each framer can be independently enabled to accept this input. This bit must
be cleared and set again to perform another counter latch.
Bit 0: Global Interrupt Pin Inhibit (GIPI).
0 = RLOF/LTCx pin indicates framer receive loss of frame
1 = RLOF/LTCx pin indicates framer loss of transmit clock
0 = Use internal IBO mux
1 = Externally wire-OR TSERs and RSERs for IBO operation
0 = Normal operation
1 = Bulk write is enabled
0 = Normal operation. Interrupt pin (INTB) will toggle low on an unmasked interrupt condition.
1 = Interrupt inhibit. Interrupt pin (INTB) is forced high (inactive) when this bit is set.
—
7
0
GTCR1
Global Transceiver Control Register 1
0F0h
—
6
0
RLOFLTS
5
0
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GIBO
0
4
—
3
0
BWE
2
0
GCLE
1
0
GIPI
0
0