ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 86

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

9.
Thirteen address bits are used to control the settings of the registers. The address map is compatible with the
Dallas Semiconductor octal framer product, DS26528 and DS26401.
The registers control functions of the framers, LIU, and BERT within the DS26524. The map is divided into four
framers, followed by four LIUs and four BERTs. Global registers (applicable to all four transceivers and BERTs) are
located within the address space of Framer 1.
The bulk write mode is a special mode to write all four transceivers with one write command (see the
register).
The register details are provided in the following tables. The framer registers bits are provided for Framer 0, and
address bits A[11:8] determine the framer addressed.
9.1
Table 9-1. Register Address Ranges (in Hex)
CHANNEL
CH1
CH2
CH3
CH4
—
DEVICE REGISTERS
Register Listings
Figure 9-1
REGISTERS
00F0–00FF
GLOBAL
shows the register map.
—
—
—
—
0000–00EF
0200–02EF
0400–04EF
0600–06EF
RECEIVE
FRAMER
—
86 of 273
TRANSMIT
0100–01EF
0300–03EF
0500–05EF
0700–07EF
FRAMER
—
1000–101F
1020–103F
1040–105F
1060–107F
LIU
—
1100–110F
1110–111F
1120–112F
1130–113F
BERT
—
GTCR1