ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 237

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Figure 10-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode
RSYNC
SYSCLK
RSER
RSYNC
RSER
RSER
RSER
RSIG
RSIG
RSIG
RSIG
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. 16.384 MHz bus configuration.
4. RSYNC is in the input mode (RIOCR.2 = 0).
5. Shows system implementation with multiple DS26528 cores driving the backplane.
6. Though not shown, RCHCLK continues to mark the channel LSB for the framers active period.
7. Though not shown, RCHBLK continues to mark the blocked channels for the framers active period.
1
2
3
1
2
3
4
Ch1-32
Ch1-32
FR2 CH1-32
FR2 CH1-32
FR4
FR4
Framer 3, Channel 32
Framer 3, Channel 32
Ch1-32
Ch1-32
FR1 CH1-32
FR1 CH1-32
FR5
FR5
A
Ch1-32
FR3 CH1-32
Ch1-32
FR3 CH1-32
B
FR6
FR6
C/A D/B
Ch1-32
Ch1-32
FR7
FR7
LSB MSB
Ch1-32
Ch1-32
FR0 CH1-32
FR0 CH1-32
FR0
FR0
Ch1-32
Ch1-32
FR0 CH1-32
FR0 CH1-32
FR1
FR1
Framer 0, Channel 1
Framer 0, Channel 1
Ch1-32
Ch1-32
FR1 CH1-32
FR1 CH1-32
FR2
FR2
A
BIT DETAIL
Ch1-32
Ch1-32
FR3
FR3
B
237 of 273
Ch1-32
Ch1-32
C/A D/B
FR2 CH1-32
FR2 CH1-32
FR4
FR4
LSB MSB
Ch1-32
Ch1-32
FR1 CH1-32
FR1 CH1-32
FR5
FR5
FR3 CH1-32
FR3 CH1-32
Ch1-32
Ch1-32
FR6
FR6
Framer 0, Channel 2
Framer 0, Channel 2
Ch1-32
Ch1-32
FR7
FR7
Ch1-32
Ch1-32
FR0 CH1-32
FR0 CH1-32
A
FR0
FR0
DS26524 Quad T1/E1/J1 Transceiver
B
Ch1-32
Ch1-32
FR0 CH1-32
FR0 CH1-32
FR1
FR1
C/A D/B
FR1 CH1-32
LSB MSB
Ch1-32
Ch1-32
FR1 CH1-32
FR2
FR2
Ch1-32
Ch1-32
FR3
FR3
Ch1-32
Ch1-32
FR2 CH1-32
FR2 CH1-32
FR4
FR4
Ch1-32
Ch1-32
FR1 CH1-32
FR1 CH1-32
FR5
FR5
A
FR3 CH1-32
Ch1-32
Ch1-32
FR3 CH1-32
B
FR6
FR6
Ch1-32
Ch1-32
FR7
FR7