ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 175

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are real-time (not latched). See
Bit 3: Loss of Receive Clock Condition (LORC). Set when the RCLK pin has not transitioned for one channel
time.
Bit 2: Spare Code Detected Condition (LSP). Set when the spare code as defined in the
registers is being received.
Bit 1: Loop-Down Code Detected Condition (LDN). Set when the loop-down code as defined in the
T1RDNCD1:T1RDNCD2
Bit 0: Loop-Up Code Detected Condition (LUP). Set when the loop-up code as defined in the
T1RUPCD1:T1RUPCD2
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are real-time (not latched). See
Bit 3: Loss of Receive Clock Condition (LORC). Set when the RCLK pin has not transitioned for one channel
time.
Bit 1: V5.2 Link Detected Condition (V52LNK). Set on detection of a V5.2 link identification signal (G.965).
Bit 0: Receive Distant MF Alarm Condition (RDMA). Set when bit 6 of time slot 16 in frame 0 has been set for
two consecutive multiframes. This alarm is not disabled in the CCS signaling mode.
—
—
7
0
7
0
register is being received.
register is being received.
RRTS3 (T1 Mode)
Receive Real-Time Status Register 3
0B2h + (200h x n): where n = 0 to 3, for Ports 1 to 4
RRTS3 (E1 Mode)
Receive Real-Time Status Register 3
0B2h + (200h x n): where n = 0 to 3, for Ports 1 to 4
—
—
6
0
6
0
—
—
5
0
5
0
RRTS3
RRTS3
175 of 273
for E1 mode.
for T1 mode.
—
—
0
0
4
4
LORC
LORC
3
0
3
0
LSP
—
2
0
2
0
V52LNK
LDN
T1RSCD1:T1RSCD2
1
0
1
0
RDMA
LUP
0
0
0
0