ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 240

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ds26524

Manufacturer Part Number
ds26524
Description
Ds26524 Quad T1/e1/j1 Transceiver
Manufacturer
Maxim Integrated Products, Inc.
Datasheet

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Figure 10-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
TCHBLK
TSYSCLK
TSSYNC
TCHCLK
TSER
TSIG
NOTE 1: TSER DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS IGNORED.
NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNELS 31 AND 1.
NOTE 3: THE F-BIT POSITION FOR THE T1 FRAME IS SAMPLED AND PASSED THROUGH THE TRANSMIT-SIDE
ELASTIC STORE INTO THE MSB BIT POSITION OF CHANNEL 1. (NORMALLY THE TRANSMIT-SIDE FORMATTER
OVERWRITES THE F-BIT POSITION UNLESS THE FORMATTER IS PROGRAMMED TO PASS THROUGH THE F-BIT
POSITION).
2
1
CHANNEL 31
CHANNEL 31
A
B
C/A D/B
LSB MSB
240 of 273
CHANNEL 32
CHANNEL 32
A
B
C/A D/B
LSB
F
3
CHANNEL 1
CHANNEL 1
A

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